1. Technical Field
The present invention relates generally to photoresist schemes for semiconductor device fabrication, and more particularly, to a multiple layer resist scheme using etch recipes particular to each layer.
2. Related Art
In the semiconductor industry, achieving critical dimensions on structure is a continuing challenge as devices become smaller. One particular area that presents significant challenges relates to thin-wire line level (single) damascene processing of hydrogenated silicon oxy-carbide (SiCOH) based films for 90 nm and beyond technologies. More particularly, conventional single layer resist schemes do not provide the mechanisms necessary to achieve the required critical dimensions. For example, current technology may require target final critical dimension (FCD) values of 115 nm and 140 nm for the metal 1 (Ml) level and the Mx+1 levels (x=1 to 5), respectively. Furthermore, current technology has desirable feature profiles such as 90° sidewalls, negligible hardmask faceting, and target line heights, which are difficult to achieve with current single layer resist schemes. The combination of utilizing a relatively thin layer of photoresist (300 nm) and etching a relatively robust carbon containing film (e.g., SiCOH) for the metal levels, i.e., Ml and Mx+1 levels (x=1 to 5), renders a particularly narrow resist budget for achieving the aforementioned objectives. Multiple layer resist schemes (bi-layer for example) have been applied to dual damascene processing, where they are required for but are limited by the application of a single etch recipe.
In view of the foregoing, there is a need in the art for an improved resist scheme to achieve the requisite critical dimensions.